TOKYO – Three-dimensional integrated circuit (3D IC) packaging saves space and materials and is vastly more energy-efficient than previous 2D technology.
Instead of laying out flat (thus 2D) a horizontally interconnected assortment of chips, each in its own minute “package” or box to protect it from corrosion, more advanced technology now stacks chips vertically (thus 3D) in a single, likewise tiny box, whose contents form a whole system.
Such 3D IC packaging is not brand new, having been used in memory and mobile devices for several years. But it is advancing rapidly and is of increasing relevance as the features of the smallest unit needing to be included in the package, the diced bit of a wafer called a die, shrink to 3-nanometer and smaller nodes.
Of course, political strategists worry about competition from China. However, the hot recent developments involve a Japan-Taiwan tie-up.
In February, the Taiwanese and Japanese press reported that Taiwan’s world-leading semiconductor foundry, TSMC, was planning to establish a R&D center in Japan’s science city of Tsukuba to develop 3D IC packaging materials in cooperation with its Japanese suppliers.
Then, at the end of May, Japan’s Ministry of Economy, Trade and Industry (METI) and its subsidiary organization, the National Institute of Advanced Industrial Science and Technology (AIST), announced that more than 20 Japanese companies would work with TSMC Japan’s 3D IC R&D Center.
METI’s announcement received a lot of attention in Japan and Taiwan, but less attention in the United States and elsewhere. It is timely to consider its implications in the context of the burst of industry awareness in Washington.
The recently released White House report entitled “Building Resilient Supply Chains, Revitalizing American Manufacturing and Fostering Broad-based Growth” pays considerable attention to advanced semiconductor packaging and materials, stating that:
As chips become increasingly complex, advanced packaging methods represent a potential area for significant technological advances. However, the United States lacks the necessary materials ecosystem and is also not a cost-effective location to develop a robust advanced packaging sector while massive Chinese investments threaten to upend the market.Italics are mine
It’s that last phrase that bothers me. In my opinion, it would make more sense to tone down the China paranoia and understand that back end semiconductor processing technology, like the front end, is led by Taiwan, Japan and South Korea.
Translation: Assembly, test and packaging are referred to as the “back end” of the semiconductor manufacturing process. Semiconductor fabrication on silicon and other types of wafers is the “front end.”
America is very strong in semiconductor tests, while legacy assembly and packaging can be done anyplace where costs are low.
According to TSMC, a 3D IC package (see diagram above) may combine high bandwidth memory (HBM) and “system-on-chip” (SoC) ICs. An SoC combines the elements of a computing or electronic system such as a central processing unit (CPU), memory, etc, that were originally separate chips.
SoIC is TSMC’s version of SoC. According to TSMC, SoIC “features ultra-high-density-vertical stacking” for high performance, low power use and minimum resistance-inductance-capacitance. In other words, a SoIC is an advanced SoC.
Media reports following METI’s announcement have mentioned only a few of the Japanese companies chosen to work with TSMC, but to understand the challenge faced by America’s new techno-nationalists, it is useful to look at most of them. (Even METI’s website does not provide a complete list.) They include:
The list of materials-making companies includes Asahi Kasei, Ibiden, JSR, Shin-Etsu Chemical, Shinko Electric Industries, Sumitomo Chemical, Sekisui Chemical, Tokyo Ohka, Nagase & Co., Nitto Denko, Nippon Electric Glass, Fujifilm, Showa Denko Materials (formerly Hitachi Chemical) and Mitsui Chemical.
On the list of equipment-makers are Keyence, Shibaura Mechatronics, Shimadzu, Showa Denko, Disco, Toray Engineering, Nitto Denko and Hitachi High-Tech.
METI also mentions the names of 17 companies working on other projects aimed at developing advanced back-end semiconductor processing technology in Japan. These projects are led by Japan’s Research Association for Advanced Systems (RaaS), Sony Semiconductor Solutions, Showa Denko Materials and Sumitomo Bakelite.
This other projects list includes the three corporate project leaders plus Screen Holdings, Daikin, Fujifilm, Panasonic Smart Factory Solutions, Ajinomoto Fine-Techno, Uyemura, Ebara, Shinkawa, Dai Nippon Printing, Disco, Tokyo Ohka, TOWA, Namics and Yamaha Robotics. Note that there is some overlap with TSMC’s partners.
All of these companies are industry leaders with significant or dominant market shares in products crucial to the semiconductor industry. They supply not only TSMC, but Intel, Samsung and the semiconductor industry worldwide.
They do have competitors – in America, Europe, Taiwan, South Korea and, to a lesser degree, China. But replacing them is not a simple matter of politicians declaring Buy American, Buy Korean or Buy Chinese. Their market position is the result of decades of experience, first-rate manufacturing, highly competent employees and long-term relationships with customers.
Japan has the most comprehensive back-end supply chain in the world. TSMC could not put together a team like this anywhere else.
In a recent article, entitled “US industrial policy not a threat to Asian allies: Biden signals new supply chain policy has more upside than downside for East Asian suppliers who get with the program,” I concluded that in general, America’s East Asian allies need not worry too much about America’s turn toward industrial policy.
This is also true in the specific case of advanced semiconductor packaging. America can, should and most probably will step up its efforts in this field, but it couldn’t go it alone even if it wanted to. If anything, the structure of the industry reinforces the need for strong alliances in East Asia.
TSMC’s 3D IC R&D Center in Japan is its first semiconductor packaging facility outside Taiwan. TSMC is planning to build front-end wafer fabrication facilities in America, but when it comes to the development of leading-edge packaging technology, it is the Taiwan-Japan alliance that counts.
Scott Foster is an analyst with Lightstream Research, Tokyo.