Posted inChips wars

TSMC eyes 3D chip packaging edge in Japan

TOKYO – Three-dimensional integrated circuit (3D IC) packaging saves space and materials and is vastly more energy-efficient than previous 2D technology. Instead of laying out flat (thus 2D) a horizontally interconnected assortment of chips, each in its own minute “package” or box to protect it from corrosion, more advanced technology now stacks chips vertically (thus […]