New US Department of Commerce regulations prevent global semiconductor firms from selling chips to Chinese tech giant Huawei if American equipment, intellectual property or software was used in their manufacturing. But do the trade restrictions mean the “end of Huawei”, as some commentators have suggested, or might there be sufficient leeway to maneuver around the newly imposed constraints? Approaching such questions requires a closer look at Huawei’s main products and corresponding supply chains. As of 2018, Huawei’s key products included networking equipment, cloud computing gear and smartphones (see figure below). All three product categories fit under the umbrella of advanced electronics, which today depend on a complex division of labor. Key components of corresponding supply chains involve (1) product design and integration; (2)
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New US Department of Commerce regulations prevent global semiconductor firms from selling chips to Chinese tech giant Huawei if American equipment, intellectual property or software was used in their manufacturing.

But do the trade restrictions mean the “end of Huawei”, as some commentators have suggested, or might there be sufficient leeway to maneuver around the newly imposed constraints?

Approaching such questions requires a closer look at Huawei’s main products and corresponding supply chains. As of 2018, Huawei’s key products included networking equipment, cloud computing gear and smartphones (see figure below).

All three product categories fit under the umbrella of advanced electronics, which today depend on a complex division of labor. Key components of corresponding supply chains involve (1) product design and integration; (2) chip design of key processors; (3) chip manufacturing; and (4) provision of chip manufacturing equipment.

Huawei Annual Report 2018

For many of Huawei’s products, the first two steps ‑ overall product design as well as chip design ‑ take place inhouse. Specifically, Huawei’s wholly-owned subsidiary HiSilicon creates chip designs optimized for Huawei’s products.

Such designs are typically tailored to the production processes of TSMC, a Taiwan-based chipmaker and long-time supplier of Huawei. TSMC, in turn, relies on tooling from a large number of US and European firms.

The latter part of this supply chain is now affected and will effectively be disrupted by the latest US trade restrictions. Because of TSMC’s dependence on US equipment, it can no longer take chip orders for Huawei.

Alternatives to TSMC are scarce, particularly alternatives without US-made content. Within China, SMIC and Tsinghua Unigroup operate semiconductor manufacturing plants at relevant scales. However, to date, neither of them can match TSMC’s technological edge.

In recent decades, Chinese players have gradually developed world-class capabilities in downstream activities of the electronics industry such as overall product and chip design. However, China continues to rely on access to global markets for upstream activities such as chip manufacturing.

Even worse for Huawei, American diplomats also placed pressure on European firms such as ASML to hold back tooling sales to Chinese chipmakers, making it harder to upgrade indigenous capabilities.  Those dual US pressures are what triggered some observers to lament the impending doom of Huawei, and possibly of the broad Chinese electronics industry.

However, such dire predictions may be premature and underestimate the complexity of the situation, including the technological and strategic degrees of freedom that are still available to Huawei. A more sober assessment starts with the distinction between near-term, medium-term and long-term implications for Huawei.

Since the new regulations involve a grace period of several months, Huawei is reported to be stockpiling inventory to last at least until the end of 2020. Beyond that, the trade restrictions will be most impactful for those products that have been designed already – with state-of-the-art equipment from TSMC in mind – and that are now awaiting production.

This is specifically the case for the Tiangang chipset which represents the tailormade heart of Huawei’s 5G base stations. Here, Huawei sits on close to 100 contracts with mobile phone carriers across the globe for station rollouts.

Huawei’s Carrier Business Group President Ryan Ding shows the Tiangang chipset at a presentation in January 2019. Photo: AFP 

The Tiangang chipset was designed for the so-called 7 nanometer (nm) node manufacturing process which TSMC has already implemented but Chinese domestic chipmakers have not. For such products, Huawei’s options boil down to either finding alternative international suppliers capable of the 7nm process or boosting the capabilities of Chinese partners.

As for the first option, Asia Times and others have pointed to the possibility of a dedicated 7nm production line operated by South Korea’s Samsung with only European and Asian equipment.

While this could elegantly address Huawei’s needs while maintaining compliance with US regulations, it remains unclear how scalable such an approach would be. It would also create dependence on one of Huawei’s fiercest rivals in the smartphone business.

As for the second option, the largest Chinese fab, SMIC, has already supplied Huawei with chips based on SMIC’s existing 14nm node process (two generations behind the state-of-the-art 7nm process, which corresponds to a technology gap of about four years).

SMIC is now working on its own version of a 7nm node manufacturing process based on existing equipment, which they refer to as the “N+1” process. First production runs are expected to start later this year.

However, it is not clear to what extent SMIC also relies on US equipment, meaning it could potentially fall under the same US ban that is causing Huawei’s problem with TSMC in the first place.

A truly domestic solution for Huawei would therefore require the localization of the semiconductor supply chain on a broader scale, including for upstream manufacturing equipment.

In working toward a fully Chinese semiconductor supply chain, photolithography machines are the central concern. These machines are needed to imprint onto silicon wafers the computer-designed transistor patterns that determine a chip’s behavior.

Advanced manufacturing processes like the 7nm node require photolithography at very high resolution. This, in turn, requires laser light of short wavelengths such as ultraviolet light.

EUV lithography equipment in a file photo. Source: Cymer

Until recently, corresponding cutting-edge equipment was referred to as “deep ultraviolet” (DUV) equipment. However, since the late 2010s, the industry-standard has evolved to “extreme ultraviolet” (EUV) with even shorter wavelength laser light and therefore finer chip features.

To date, the production of commercial EUV lithography machines has only been mastered by a single firm: Holland-based ASML. TSMC opted to use EUV equipment, provided by ASML, for its 7nm process. However, DUV also still remains an option at this scale. Consequently, both EUV and DUV research efforts in China should interest Huawei.

Changchun-based CIOMP and Shanghai-based SMEE stand out in this regard.  

CIOMP is a research institute under the Chinese Academy of Sciences and has been involved in EUV research since the 1990s. Researchers are reportedly working on a Chinese 125W EUV lithography machine aimed to be ready for deployment in about two years. It is difficult to predict whether such schedules can be met and whether the equipment would perform as needed.

SMEE is China’s leading supplier of DUV equipment and is reportedly set to release a DUV lithography machine capable of meeting 28nm node requirements later this year. Once such equipment is deployed, some industry observers expect steady improvement down to the 14nm and 7nm nodes.

Such developments suggest a possible medium-term option for Huawei that consists of working closely with local chipmakers such as SMIC as well as local equipment suppliers such as SMEE and CIOMP. Perhaps the most realistic approach would involve a 7nm node manufacturing line operated by SMIC with DUV lithography equipment from SMEE.

Despite such possible options, would an existing knowledge gap not persist, or even widen, given the imposed constraints? One might wonder whether, by the time Chinese firms arduously reach the 7nm node, others will have marched ahead to a hypothetical 1nm node.

Such considerations might indeed be justified if the rapid progression to new nodes were to continue, as was the case over much of the past five decades. However, since the early 2010s, there has been a slowdown of Moore’s Law – the prediction that chip density doubles every 18-24 months – and the associated introduction of new nodes.

Following the 7nm node, experts expect two more nodes – 5nm and 3nm – beyond which the future is highly uncertain. Each of these nodes might involve just about another 20% performance improvement or size reduction, a modest number compared to the larger, more frequent jumps of the past.

Source: Sigarch.org

The impending standstill might be caused by nothing less than the laws of physics. For the 3nm node process, the expected feature size of transistor components gets down to the order of 30nm.

At such short distances, quantum effects like tunneling start to kick in and as a result transistors end up leaking. Further miniaturization could then require a fundamental redesign of the transistor, which experts believe may take decades.

For Huawei and the Chinese semiconductor industry, this is good news in a certain sense: a fundamental redesign of the transistor would level the playing field. If nothing else, the end of Moore’s Law represents a fixed point against which existing incumbent leads would eventually whittle away.

The above considerations focus on the impact of recent trade restrictions on Huawei’s most vulnerable business: state-of-the-art chip designs that are currently awaiting production.

However, in practice, electronics firms like Huawei develop and sell products that draw on a range of different manufacturing processes, with only some of them corresponding to the latest generation.

This is also reflected in the order books of chip makers such as TSMC. The figure below shows the distribution of manufacturing processes corresponding to orders in early 2020.

Whereas about one-third of the produced chips correspond to the latest standard, i.e. the 7nm node, two-thirds do not. New nodes typically enable smaller chips and lower power consumption on the order of 20-40% compared to the previous node.

Source: TSMC Quarterly Results Presentation

However, opting instead for a mature manufacturing process offers advantages such as lower production costs due to amortized equipment, less risk of production delays and greater flexibility in the choice of vendors.

How such advantages stack up against greater chip density depends on the particular product. Chip density is important for smartphones but less so in automotive products or in network equipment where space and power constraints are not as stringent.

The latter fact is, of course, of no benefit now for Huawei’s latest 5G base stations as they have already been designed around the 7nm process. However, for future products, engineers may want to evaluate carefully whether designing for a 14nm node process might yield certain benefits, in effect trading off chip density against supply chain flexibility.

But chip density is but one of several factors that determine overall chip performance. With the steady advancement of miniaturization, chip density was a low hanging fruit which chip designers relied upon with convenient regularity. However, with Moore’s Law drawing to an end, engineers need to think more broadly about performance optimization.

Performance gains can also be achieved by focusing on higher layers of the so-called hardware-software stack. This includes the optimization of chip architectures, or the structure of chips, as well as the codes that run on them.

A recent Science Magazine article illustrates the potential of such optimization: as a result of software and hardware tweaks, researchers at MIT were able to demonstrate speedups of several orders of magnitude in common operations such as matrix multiplication. 

Alternative mechanisms for performance improvement include optimized thermal management as well as specialized hardware acceleration tailored to frequently used algorithms like those used in image recognition (see neuromorphic engineering).

The article concludes that “performance-engineering of software, development of algorithms, and hardware streamlining…can continue to make computer applications faster in the post-Moore era, rivaling the gains accrued over many years by Moore’s law.”

A chip from Huawei subsidiary HiSilicon on promotional display. Photo: Facebook/ImagineChina

In other words, with enough dedication, it should be possible for an optimized 14nm chip to outperform an ordinary 7nm chip.

Developing new manufacturing equipment such as  the machines needed for EUV lithography does not apparently lie within the realm of Huawei’s R&D expertise. However, exploring alternative ways of optimizing chip designs, software and electronic product architectures lie at its very heart.

The fact that Huawei’s R&D expenditures – on the order of US$19 billion in 2019 – dwarf those of its network equipment competitors such as Ericsson, Nokia, and Cisco suggests further potential for creative adaptation to the new constraints.

Finally, in Huawei’s smartphone business, chips are more standardized compared to the specialized network equipment sector. Here, a worst-case scenario could involve the purchase of off-the-shelf processors from other chip vendors.

Such chips could then be integrated into various Huawei smartphone and tablet designs as has been done previously. This would certainly mean lower margins for Huawei but it might be a worthwhile price to pay to maintain market share in consumer markets and ensure the company’s upward trajectory in the face of mounting US pressure.

Florian Metzler is a Postdoctoral Associate with the MIT Department of Materials Science and Engineering and the MIT Research Laboratory of Electronics. He holds degrees in Engineering Systems, Nuclear Science and Engineering, Technology Policy and Electronic Engineering from MIT and HKUST. He has taught graduate courses on Technology Management and consulted with companies and agencies in the US, Asia and Europe.